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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2005, zarlink semiconductor inc. all rights reserved. features ? nordig ii and etsi 300 744 compliant ? superior single frequency network performance ? unique active impulse-noise filtering ? single saw operation ? automatic co-channel and adjacent-channel interference suppression ? clock generation from single low-cost 20.48 mhz crystal or external 4 or 27 mhz clock ? if sampling at 4.57, 36.17 or 43.5 mhz from a single crystal frequency ? channel bandwidth of 6, 7 & 8 mhz ? blind acquisition capability (including 2 k / 8 k mode detect) ? automatic spectral inversion detection ? fast auto-scan and acquisition technology ? very low software overhead ? dual agc control option ? access to channel snr, pre- and post-viterbi bit error rates ? compact 64 pin lqfp ? less than 0.22 w power consumption ? standby and sleep options applications ? set-top boxes ? integrated digital televisions ? personal video recorders ? terrestrial pc reception ? mobile and portable applications zarlink evaluation kits in clude application board, tnim and supporting software based on industry standard operating systems. device dr ivers are also available enabling rapid product devel opment and reduction in time to market. description MT352 is a superior third generation coded orthogonal frequency division multiplex (cofdm) television demodulator that is both nordig ii and dvb (as defined in ets 300 744 specification) compliant. it can be used in either 2 k or 8 k modes with 6, 7 or 8 mhz channels and is capable of addressing all modes of transmission. the device includes a high performance 10-bit a/d converter capable of accepting direct if at 36.17 or 43.75 mhz. sampling rates required for both these frequencies in 6,7 or 8 mhz ofdm channels can be generated from a single 20.48 mhz crystal. alternatively, there is provision to replace this crystal with a 4 or 27 mhz external clock input. february 2005 ordering information MT352/cg/gp1n 64 pin lqfp trays MT352/cg/gp1q 64 pin lqfp tape & reel MT352/cg/gp2q 64 pin lqfp* tape & reel MT352/cg/gp2n 64 pin lqfp* trays * pb free matte tin 0 o c to +70 o c MT352 cofdm demodulator data sheet figure 1 - block diagram rf in adc agc secondary tuner control impulse suppression if to baseband conversion & interpolator fft symbol, carrier & timing recovery pilot & channel processor control engine symbol & bit de-interleaver & demapper fec mpeg ts 2-wire bus primary 2-wire bus
MT352 data sheet 2 zarlink semiconductor inc. unique algorithms that actively filt er out impulse noise, without affe cting normal performance, have been implemented. this reduces the interference effect from ve hicles and electrical appliances, which is known to have significant detrimental effect on t he quality of digital tv reception. programming is simplified utilizing a high level command driven interface. a sophisticated engine controls all acquisition and tracking operations as well as contro lling the tuner via a 2-wire bus. any frequency range can be automatically scanned for digi tal tv channels. this mec hanism ensures minimal intera ction, maximum flexibility, fastest acquisition and the fast est auto scan capability of any chip in the market. blind acquisition mode enables automatic detection of all ofdm signal parameters, including mode, guard and spectral inversion. the frequency capture range is sufficient to compensate for the combined offset introduced by the tuner and broadcaster. the device is packaged in a 64 pin lqfp and consumes less than 220 mw of power. figure 2 - package outline MT352 cg yyww *w ? ? pin 1 corner
MT352 data sheet 3 zarlink semiconductor inc. pin description pin description table pin no name description i/o type v ma mpeg pins 47 mostrt mpeg packet start o cmos tristate 33 1 48 moval mpeg data valid o 33 1 49-53, 56-58 mdo(0:7) mpeg data bus o 33 1 61 moclk mpeg clock out o 33 1 62 bkerr block error o 33 1 63 miclk mpeg clock in i cmos 33 11 status status output o 33 1 6irq interrupt output o open drain 5 6 control pins 4 clk1 serial clock i cmos 5 5 data1 serial data i/o open drain 5 6 23 xti low phase noise oscillator i cmos 24 xto o 10 sleep device power down i 33 12, 15-18 sadd(4:0) serial address set i 33 44 smtest scan mode enable i 33 35 clk2/gpp0 serial clock tuner i/o open drain 56 36 data2/gpp1 serial data tuner i/o 5 6 42 agc1 primary agc o 5 6 41 agc2/gpp2 secondary agc i/o 5 6 43 gpp(3) general purpose i/o i/o 5 6 9 reset device reset i cmos 5 27 oscmode crystal oscillator mode i cmos 33 26 plltest pll analogue test o analog inputs 30 vin positive input i 31 vin negative input i supply pins
MT352 data sheet 4 zarlink semiconductor inc. 21 pllvdd pll supply s 18 22 pllgnd s 0 7, 19, 37, 39, 59, 64 cvdd core logic power s 18 2, 13, 45, 54, vdd i/o ring power s 33 1, 3, 8, 14, 20, 25, 38, 40, 46, 55, 60 gnd core and i/o ground s 0 28 avdd adc analog supply s 18 29, 32 agnd s 0 33 dvdd adc digital supply s 18 34 dgnd s 0 pin description table (continued) pin no name description i/o type v ma
MT352 data sheet table of contents 5 zarlink semiconductor inc. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 analogue-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 automatic gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 if to baseband conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 adjacent channel filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 interpolation and clock synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6 carrier frequency synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 symbol timing synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.8 fast fourier transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.9 common phase error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.10 channel equalisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.11 impulse filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.12 transmission parameter signalling (tps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.13 de-mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.14 symbol and bit de-interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.15 viterbi decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.16 mpeg frame aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.17 de-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.18 reed-solomon decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.19 de-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.20 mpeg transport interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 software control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 2-wire bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 examples of 2-wire bus messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.3 primary 2-wire bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 mpeg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 data output header format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 mpeg data output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 mpeg output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3.1 moclkinv = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.3.2 moclkinv = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 crystal specification and exte rnal clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.0 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MT352 data sheet list of figures 6 zarlink semiconductor inc. figure 1 - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - ofdm demodulator diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4 - fec block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5 - primary interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6 - primary 2-wire bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7 - dvb transport packet header byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8 - mpeg output data waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9 - mpeg timing - moclkinv = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10 - mpeg timing - moclkinv = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11 - crystal oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12 - typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MT352 data sheet list of tables 7 zarlink semiconductor inc. table 1 - programmable address details for 2-wire bus in tnim evaluation application. . . . . . . . . . . . . . . . . . . 13 table 2 - timing of 2-wire bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3 - moclkinv = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4 - mdoswap = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5 - mdoswap = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MT352 data sheet 8 zarlink semiconductor inc. 1.0 functional description a functional block diagram of the mt 352 ofdm demodulator is shown in figure 3. this accepts an if analogue signal and delivers a stream of demodulated soft decisi on data to the on-chip viterbi decoder. clock, timing and frequency synchronization operations are all digital and t here are no analogue control loops except the agc. the frequency capture range is large enough for all practical applications. this demodulator has novel algorithms to combat impulse noise as well as co-channel and adjacent c hannel interference. if the modulation is hierarchical, the ofdm outputs both high and low priority data streams. only one of these streams is fec-decoded, but the fec can be switched from one stream to another with minimal interruption to the transport stream. figure 3 - ofdm demodulator diagram the fec module shown in figure 4 consists of a conc atenated convolutional (vit erbi) and reed-solomon decoder separated by a depth-12 convolutional de-interleaver. the viterbi decoder operates on 5-bit soft decisions to provide the best performance over a wide range of channel conditions. the trace-back depth of 128 ensures minimum loss of performance due to inevitable survivor trunc ation, especially at high co de rates. both the viterbi and reed-solomon decoders are equipped with bit-error monitors. the former provides the bit error rate (ber) at the ofdm output. the latter is the more useful measure as it gives the viterbi output ber. the error collecting intervals of these are progra mmable over a very wide range. figure 4 - fec block diagram the fsm controller shown in figure 3 above controls both th e demodulator and the fec. it also drives the 2-wire bus to the tuner. the controller facilitates the automated s earch of all parameters or any sub-set of parameters of the received signal. it can also be used to scan any defined frequency range searchi ng for ofdm channels. this
MT352 data sheet 9 zarlink semiconductor inc. mechanism provides the fast channel scan and acquisit ion performance, whilst requiring minimal software overhead in the host driver. the algorithms and architectures used in the MT352 hav e been heavily optimized to minimize hardware and chip area. this is proven by its 220 mw (typical) power consum ption, which is the lowest of any ofdm device in the market today. 1.1 analogue-t o-digital converter the MT352 has a high performance 10-bi t analogue-to-digital converter (adc) which can sample a 6, 7 or 8 mhz bandwidth ofdm signal, with its spectrum centred at: ? 4.57 mhz near-zero if ? 36.17 mhz if ? 43.75 mhz if the adc can be clocked using: ? crystal oscillator with a 20.48 mhz crystal ? 4 mhz or 27 mhz clock input an on-chip programmable phase locked loop (pll) is us ed to generate the adc sampling clock. the crystal frequency of 20.48 mhz is used for 36.17 mhz if sampling and 19.6267 mhz is used for 43.75 mhz if sampling. note that this 19.6267 mhz sampling clock can be generated from the 20.48 mhz crystal by appropriately programming the pll. hence the same 20.48 mhz crystal can support 6, 7 and 8 mhz ofdm as well as 36.17 and 43.75 mhz if. 1.2 automatic gain control an agc module compares the absolute value of the digi tized signal with a programm able reference. the error signal is filtered and is used to control the gain of the amplifier. a sigma-delta modul ated output is provided, which has to be rc low-pass filtered to obtain the voltage to co ntrol the amplifier. upper and lower limits can be set to the agc control voltage using registers. the programmable agc reference has been optimized. a large value for the reference leads to excessive adc clipping and a small value results in excessive quantiz ation noise. hence the optimum value has been determined assuming the input signal amplitude to be gaussian distribut ed. the latter is justified by applying the central limit theorem in statistics to the ofdm signal, which consists of a large number of randomly modulated carriers. this reference or target value may have to be lowered sli ghtly for some applications. slope control bits have been provided for the agcs and these have to be set correctl y depending on the gain-versus-voltage slope of the gain control amplifiers. the bandwidth of the agc is set to a large value for quick acquisition then reduced to a small value for tracking. the agc is free running during ofdm channel changes and locks to the new channel while the tuner lock is being established. this is one of the features of MT352 used to minimize acquisition time. a robust agc lock mechanism is provided and the other parts of th e MT352 begin to acquire only after the agc has locked. two agc control outputs are available, one to drive an rf amplifier and the ot her to control an if amplifier. the parameters for both loops are programmable. in the default mo de, only the if agc loop is activated. 1.3 if to baseband conversion sampling a 36.17 mhz if signal at 20.48 mhz results in a spectrally inverted ofdm signal centred at 4.79 mhz. sampling a 43.75 mhz if signal at 19.6267 mhz gives a n on-inverted signal at 4.5 mhz. the first step of the demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in baseband. a correction for spectral inversion is implemented during this conversion proces s. note also that the MT352 has control mechanisms to search automatically for an unknown spectral inversion status.
MT352 data sheet 10 zarlink semiconductor inc. 1.4 adjacent channel filtering adjacent channels, in particular the nicam digital sound signal associated with analogue channels, are filtered prior to the fft. 1.5 interpolation and clock synchronisation MT352 uses digital timing recovery and this eliminat es the need for an external vcxo. the adc samples the signal at a fixed rate, for example, 20.48 mhz. conversion of the 20.48 mhz signal to the ofdm sample rate is achieved using the time-varying interpolator. the ofdm sa mple rate is 64/7 mhz for 8 mhz and this is scaled by factors 6/8 and 7/8 for 6 and 7 mhz chann el bandwidths. the nominal ratio of the adc to ofdm sample rate is programmed in a MT352 register (defaults are for 20. 48 mhz sampling and 8 mhz ofdm). the clock recovery phase locked loop in the MT352 compensates for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock. 1.6 carrier freq uency synchronisation there can be frequency offsets in the signal at the input to ofdm, partly due to tuner step size and partly due to broadcast frequency shifts, typically 1/6 mhz. these are tracked out digitally, without the need for an analogue frequency control (afc) loop. the default frequency capture range has been set to 285 khz in the 2 k mode and 142 khz in the 8 k mode. however, these values can be doubled, if necessary, by programming an on-chip regist er. it is recommended that this larger capture range be used for channel scan in or der to find channels with br oadcast frequency shifts, without having to adjust the tuner. after the ofdm module has locked, the frequency offset can be read from an on-chip register. 1.7 symbol timing synchronisation this module computes the optimum sample position to trig ger the fft in order to el iminate or minimize inter- symbol interference in the presence of multi-path distortion. furthermore, this trigger point is continuously updated to dynamically adapt to time-variations in the transmission channel. 1.8 fast fourier transform the fft module uses the trigger information from the timi ng synchronization module to set the start point for an fft. it then uses either a 2 k or 8k fft to transform the data from the time domain to the frequency domain. an extremely hardware-efficient and highly accura te algorithm has been used for this purpose. 1.9 common phase error correction this module subtracts the common phase offset from all the carriers of the ofdm signal to minimize the effect of the tuner phase noise on system performance. 1.10 channel equalisation this consists of two parts. the first part involves es timating the channel frequency response from pilot information. efficient algorithms have been used to track time-varying channels with a minimum of hardware. the second part involves applying a correction to the data carriers based on the estimated frequency response of the channel. this module also generates dynamic channel state information (csi) for every carrier in every symbol. 1.11 impulse filtering MT352 contains several mechanisms to reduce the im pact of impulse noise on system performance.
MT352 data sheet 11 zarlink semiconductor inc. 1.12 transmission parameter signalling (tps) an ofdm frame consists of 68 symbols and a superframe is made up of four such frames. there is a set of tps carriers in every symbol and all these carry one bit of tps. these bits, when comb ined, include information about the transmission mode, guard ratio, constellation, hierarch y and code rate, as defined in ets 300 744. in addition, the first eight bits of the cell identifier are contained in even frames and the seco nd eight bits of the cell identifier are in odd frames. the tps module extracts all the tps data, and presents these to the hos t processor in a structured manner. 1.13 de-mapper this module generates soft decisions for demodulated bits using the channel-equa lized in-phase and quadrature components of the data carriers as well as per-carrier channel state information (csi). the de-mapping algorithm depends on the constellation (qpsk, 16qam or 64qam) and the hierarchy = 0, 1, 2 or 3). soft decisions for both low- and high-priority dat a streams are generated. 1.14 symbol a nd bit de-interleaving the ofdm transmitter interleaves the bits within each ca rrier and also the carriers within each symbol. the de- interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions to the fec in the original order. 1.15 viterbi decoder the viterbi decoder accepts the 5-bit soft decision data from the ofdm demodul ator and outputs a decoded bit- stream. the decoder does the de-puncturing of the input data for all code rates other than 1/2. it then evaluates the branch metrics and passes these to a 64-state path-metric upd ating unit, which in turn outputs a 64-bit word to the survivor memory. the viterbi decoded bits are obtained by tracing back the survivor paths in this memory. a trace- back depth of 128 is used to minimize any loss in performance, especially at high code rates. the decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors at its input, on the assumption t hat the viterbi output ber is signi ficantly lower than its input ber. 1.16 mpeg frame aligner the viterbi decoded bit stream is aligned into 204-byt e frames. a robust synchronization algorithm is used to ensure correct lock and to prevent loss of lock due to noise impulses. 1.17 de-interleaver errors at the viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a number of 204-byte frames to give the reed-solomon decoder a better chance of correcting these. the de- interleaver is a memory unit which implements the invers e of the convolutional interleaving function introduced by the transmitter. 1.18 reed-s olomon decoder every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a systematic (255,239) reed-solomon code. the corresponding (204,188) reed-solomon decoder is capable of correcting up to eight byte errors in a 204-byte frame. it may also detect frames with more than eight byte errors. in addition to efficiently performing th is decoding function, the reed-solomon decoder in MT352 keeps a count of the number of bit errors corrected ov er a programmable period and the nu mber of uncorrectable blocks. this information can be used to compute the post-viterbi ber.
MT352 data sheet 12 zarlink semiconductor inc. 1.19 de-scrambler the de-scrambler de-randomizes the reed-solomon decoded da ta by generating the exclusive-or of this with a pseudo-random bit sequence (prbs). this outputs 188-byt e mpeg transports packets. the tei bit of the packet header is set to indicate uncorrectable packets. 1.20 mpeg transport interface mpeg data can be output in parallel or serial mode. the output clock frequency is automatically chosen to present the mpeg data as uniformly spaced as possible to the transport processor. this frequency depends on the guard ratio, constellation, hierarchy and code rate. there is al so an option for the data to be extracted from the MT352 with a clock provided by the user. 2.0 software control acquisition of an ofdm channel and frequency scan fo r ofdm channels are contro lled by an on-chip state machine, which minimizes the software requirement in the host processor. to acquire a channel, the host programs the channel frequency in the MT352. the on-chip state mach ine then writes the frequency information to the tuner, awaits tuner lock and acquires the ofdm channel to ge nerate the transport stream. the controller can be made to automatically search for every parameter in the ofdm signal , including spectral inversion status. furthermore, this controller will re-acquire the channel in the ev ent of an interruption to the incoming signal. to scan a frequency range, the host programs the start and end frequencies for the search as well as the step size, which defaults to 8 mhz. the MT352 then automaticall y scans the frequency range by appropriately programming the tuner and searching for ofdm signals. once a channel has been located, the host is interrupted to read the channel information from the MT352. then MT352 continue s the search. by default, only the channels which can generate a reliable transport stream are reported, but there is al so provision for locating very weak channels. the frequency capture range of MT352 can be maximized to capture channels with fr equency offsets without re- programming the tuner, in both 2 k and 8 k modes. the above approach to channel acquisition and scan has resulted in very fast acquisition and scan times whilst minimizing software overhead in the host processor. furthermore, all this f unctionality has very efficiently been mapped into hardware to result in a device consuming less than 220 mw of power. 3.0 interfaces figure 5 - primary interfaces the MT352 interfaces to other parts of a terrestrial receiv er system can be partitioned into three groups: the host controller, the tuner and the mpeg dec oder. one other pin, the status output , is multi-functional and can directly
MT352 data sheet 13 zarlink semiconductor inc. drive a led to show the status of a range of different internal lock flags. alternatively, it can drive an audio transducer to give an audio frequency that is dependent upon the error rate of the received signal. this feature can be used for faster installation of a system where the aerial may need to be adjusted, as signal strength is not the best guide for the opti mum aerial position for cofdm reception. 3.1 2-wire bus 3.2 host the primary 2-wire bus serial interface uses pins: ? data1 (pin 5) serial data, the most significant bit is sent first. ? clk1 (pin 4) serial clock. the 2-wire bus address is determined by applying vdd or vss to the sadd[4:0] pins. in the current tnim evaluation application, the 2-wire bus address is 0001 111 r/ w with the pins connected as follows: when the MT352 is powered up, the reset pin 28 should be held low for at least 50ms after vdd has reached normal operation levels. as the reset pin goes high, the logic levels on sad d[4:0] are latched as the 2-wire bus address. addr[0] is the r/ w bit. the circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. in receive mode, the first data byte is written to the radd virtual register, which forms the register sub-address. the radd register takes an 8-bit value that deter mines which of 256 possible r egister addresses is written to by the following byte. not all addresses are valid and many are reserved registers that mu st not be changed from their default values. multiple byte reads or writes will auto-increment the value in radd, but care should be taken not to access the reserved registers accidentally. following a valid chip address, the 2-wire bus stop comma nd resets the radd register to 00. if the chip address is not recognized, the MT352 will ignore all activity until a vali d chip address is received. the 2-wire bus start command does not reset the radd register to 00. this allows a combined 2-wire bus message, to point to a particular read register with a writ e command, followed immediately with a read data command. if required, this could next be followed with a write command to continue from the latest address. radd would not be sent in this case. finally, a stop command should be sent to free the bus. when the 2-wire bus is addressed (after a recognized stop command) with the read bit se t, the first byte read out is the contents of register 00. 3.2.1 tuner the MT352 has a general purpose port that can be confi gured to provide a secondary 2- wire bus. master control mode is selected by a si ngle register control bit. the allocation of the pins is: gpp0 pin 35 = clk2, gpp1 pin 36 = data2. addr[7] addr[6] addr[5] addr[4] addr[3] addr[2] addr[1] not programmable sadd[4] sadd[ 3] sadd[2] sadd[1] sadd[0] vss vss vss vdd vdd vdd vdd table 1 - programmable address details for 2-wire bus in tnim evaluation application
MT352 data sheet 14 zarlink semiconductor inc. 3.2.2 examples of 2-wire bus messages write operation - as a slave receiver: read operation - MT352 as a slave transmitter: write/read operation with repeated start - MT352 as a slave transmitter: 3.2.3 primary 2-wire bus timing figure 6 - primary 2-wire bus timing where: s = start sr = restart, i.e., star t without stopping first. p = stop. key: s start condition w write (=0) p stop condition r read (= 1) a acknowledge na not acknowledge italics MT352 output radd register address s device w a radd a data a data a p address (n) (reg n) (reg n+1) sdevice radata adata adata nap address (reg 0) (reg 1) (reg 2) s device w a radd a s device r a data a data na p address (n) address (reg n) (reg n+1)
MT352 data sheet 15 zarlink semiconductor inc. note 1. the rise time depends on the external bus pull up resistor. loading prevents full speed operation. 3.3 mpeg 3.3.1 data output header format figure 7 - dvb transport packet header byte parameter symbol value unit min. max. clk clock frequency (primary) f clk 0450khz bus free time between a stop and start condition t buff 200 ns hold time (repeated) start condition t hd;sta 200 ns low period of clk clock t low 1300 ns high period of clk clock t high 600 ns set-up time for a repeated start condition t su;sta 200 ns data hold time (when input) t hd;dat 100 ns data set-up time t su;dat 100 ns rise time of both clk and data signal. t r note 1 ns fall time of both clk and data signals, (100 pf to ground) t f 20 ns set-up time for a stop condition t su;sto 200 ns table 2 - timing of 2-wire bus
MT352 data sheet 16 zarlink semiconductor inc. after decoding the 188-byte mpeg packet, it is out put on the mdo pins in 188 consecutive clock cycles. additionally when the entei bit in the config register (0x8 a) is set high (default), the tei bit of any uncorrectable packet will automatically be set to '1'. if entei bit is low then tei bit will not be changed (but no te that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output). 3.3.2 mpeg data output signals the mpegen bit in the config register must be set low to enable the mpeg data. the maximum movement in the packet synchronization byte position is limited to 1 output clock period. moclk will be a continuously running clock once symbol lock has been achieved, and is derived from the symbol clock. in figure 8, moclk is shown in with moclkinv = '1', the default state. all output data and signals (mdo[7:0], mostrt, moval & bkerr ) change on the negative edge of moclk (moclkinv = 1) to present stable data and signals on the positi ve edge of the clock. a complete packet is output on mdo[7:0] on 188 consecutiv e clocks and the mdo[7:0] pins will remain low during the inter-packet gaps. mostrt goes high for the first byte clock of a packet. moval goes high on the first byte of a packet and remains high until the last byte has been clocked out. bkerr goes low on the first byte of a packet where uncorrectable bytes are detected and will remain low until the last byte has been clocked out. figure 8 - mpeg output data waveforms 3.3.3 mpeg output timing maximum delay conditions: vdd = 3.0 v, cvdd = 1.62 v, tamb = 70 o c, output load = 10 pf minimum delay conditions: vdd = 3.6 v, cvdd = 1.98 v, tamb = 0 o c, output load = 10 pf moclk frequency = 61.44 mhz.
MT352 data sheet 17 zarlink semiconductor inc. 3.3.3.1 moclkinv = 1 the setup time is due to the delay on mostrt, moval and bkerr . mdo[0] is faster since it uses a stronger output driver cell. figure 9 - mpeg timing - moclkinv = 1 3.3.3.2 moclkinv = 0 mdoswap = 0 parameter maximum delay conditions minimum delay conditions data output delay t d 7 ns 0.3 ns setup time t su 0.5 ns 5 ns hold time t h 8 ns 8 ns table 3 - moclkinv = 1 parameter maximum delay condit ions minimum delay conditions data output delay t d 8 ns 0.7 ns setup time t su 8 ns 15 ns hold time t h 1.5 ns 0.5 ns table 4 - mdoswap = 0
MT352 data sheet 18 zarlink semiconductor inc. the hold time is due to the fast output on mdo[0]. if md oswap is set to 1 the data output is on mdo[7] which has a slower driver. this improves the hold time: mdoswap = 1 figure 10 - mpeg timing - moclkinv = 0 parameter maximum delay condit ions minimum delay conditions data output delay t d 8 ns 0.7 ns setup time t su 8 ns 15 ns hold time t h 3 ns 1.2 ns table 5 - mdoswap = 1
MT352 data sheet 19 zarlink semiconductor inc. 4.0 electrical characteristics 4.1 recommended operating conditions 4.2 absolute maximum ratings note: stresses exceeding these listed under absolute maximum ratings may induce failure. exposure to absolute maximum ratings fo r extended periods may reduce reliability. function ality at or above these co nditions is not implied. recommended operating conditions table parameter symbol min. typ. max. units power supply voltage: periphery vdd 30 33 36 v core cvdd 162 18 198 v power supply current: periphery 1 1. current from the 33 vv supply will be mainly dependent on the external loads. idd p 1ma core idd c 120 ma input clock frequency 2 2. the min/max frequ encies given are those supported by the oscilla tor cell. frequencie s outside these limits are acceptable w ith an external clock signal. xti 1600 2048 2500 mhz clk1 primary serial clock frequency fclk 450 khz ambient operating temperature 0 70 c adc input impedance @ 36 mhz 2 k ? absolute maximum ratings table parameter symbol min. max. unit power supply vdd -0.3 +3.6 v cvdd -0.3 +2.0 v voltage on input pins (5 v rated) vi -0.3 5.5 v voltage on input pins (3.3 v rated) vi -0.3 vdd + 0.3 v voltage on output pins (5 v rated) vo -0.3 5.5 v voltage on output pins (3.3 v rated) vo -0.3 vdd + 0.3 v storage temperature tstg -55 150 c operating ambient temperature top 0 70 c junction temperature tj 125 c
MT352 data sheet 20 zarlink semiconductor inc. 4.3 dc electrical characteristics parameter conditions pins symbol min. typ. max. unit operating voltage periphery vdd 3.0 3.3 3.6 v core cvdd 1.62 1.8 1.98 v supply current 1.62 > cvdd > 1.98 idd- core 120 ma supply current sleep mode 200 a outputs output levels ioh 2 ma 3.0 > vdd > 3.6 mdo(7:0), moval, mostrt, moclk, status, bkerr voh 2.4 v iol 2 ma 3.0 > vdd > 3.6 vol 0.4 v iol 6 ma 3.0 > vdd > 3.6 gpp(3:0), data1, agc1, agc2, irq vol 0.4 v output capacitance not including track mdo(7:0), moval, mostrt, moclk, status, bkerr 3.0 pf gpp(3:0), data1, agc1, agc2 irq 3.6 pf output leakage (tri-state) 1 a inputs input levels 3.0 > vdd > 3.6 -0.5 vin vdd+0.5 v miclk, sadd(4:0), sleep, osc- mode vih 2.0 v input levels 3.0 > vdd > 3.6 -0.5 vin +5.5 v gpp(3:0), clk1, data1, reset vih 2.0 v input levels 3.0 > vdd > 3.6 capacitances do not include track all inputs vil 0.8 v input leakage current sleep, smtest, miclk, clk1, oscmode 1 a input capacitance 1.8 pf input capacitance sadd(4:0), data1, gpp(3:0) 3.6 pf
MT352 data sheet 21 zarlink semiconductor inc. 4.4 crystal specificat ion and extern al clocking parallel resonant fundamental frequency (preferred) 20.4800 mhz tolerance over operating temperature range 25 ppm tolerance overall 50 ppm typical load capacitance 27 pf drive level 0.4 mw max. equivalent series resistance <50 ? figure 11 - crystal oscillator circuit xti xto xt1 c2 oscmode c1
MT352 data sheet 22 zarlink semiconductor inc. 5.0 application circuit figure 12 - typical application circuit

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